Since the invention of the integrated circuit, the semiconductor industry has experienced continual rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing for the integration of more components into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit resistance-capacitance (RC) delay and power consumption increase.
Three-dimensional integrated circuits (3D IC) are therefore created to resolve the above-discussed limitations. In a typical formation process of 3D IC, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Deep vias are then formed to interconnect devices on the first and second wafers.
Much higher device density has been achieved using 3D IC technology, and up to six layers of wafers have been bonded. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D IC technology has the potential of being the mainstream technology of the next generation.
Conventional methods for forming 3D IC also include die-to-wafer bonding, wherein separate dies are bonded to a common wafer. An advantageous feature of the die-to-wafer bonding is that the size of the dies may be smaller than the size of chips on the wafer.
Recently, through-silicon vias, also referred to as through-wafer vias, are increasingly used as a way of implementing 3D IC. FIG. 1 illustrates a conventional 3D IC including through-silicon vias, wherein bottom wafer 2 is bonded to top wafer 4. Both wafers 2 and 4 include integrated circuits (not shown). The integrated circuits in bottom wafer 2 are connected to the integrated circuits in wafer 4 through interconnect structures 6 and 8. The integrated circuits in wafers 2 and 4 are further connected to external pads 12 through through-silicon vias 10. The structure shown in FIG. 1 is typically referred to as having a pads-on-top structure, indicating that external pads 12 are formed on top of the stacked wafers.
Typically, before the stacked wafers are sawed, the chips in the stacked wafers are probed using probe head 16. Chip probing is a wafer level technology for determining the quality of dies on wafers. The chips are tested before they are sawed from wafers, and only those chips that pass the probe tests are packaged. By identifying problematic chips at an early stage, packaging costs are saved. In the structure shown in FIG. 1, bottom wafer 2 is not thinned, and thus the illustrated structure is robust enough to sustain the probing process.
With the increasing demand of high-density integrated circuits, more layers of wafers/dies need to be stacked together, and thus a structure shown in FIG. 2 is explored. In this structure, dies 22 and 24 are stacked on bottom wafer 20, wherein each of the dies 22, 24 and bottom wafer 20 includes integrated circuits. Besides through-silicon vias 26 formed in dies 22, through-silicon vias 28 are also formed in bottom wafer 20 and connected to pads 30, on which ball grid array balls 32 are mounted. The structure shown in FIG. 2 is typically referred to as a pads-on-bottom structure. Since through-silicon vias can only be formed in thin wafers, bottom wafer 20 needs to be thinned. This results in a structure too thin for the chip probing. For example, dies 22 and 24 may have a thickness of about one mil, and bottom wafer 20 may have a thickness of about 3 mils. The thin stack structure is advantageous for building highly integrated circuits. However, the total thickness of 5 mils is not thick enough for the chip probing, which may break the stack structure. Typically, the stack structures formed on eight-inch wafers preferably have a total thickness of greater than about 19 mils. The stack structures formed on twelve-inch wafers preferably have a total thickness of greater than about 21 mils. The conflicting requirements for the thicknesses of the stack structure cause a dilemma.
Accordingly, what is needed in the art is a structure and formation methods for forming 3D IC having through-silicon vias, so that both the reliability of the manufacturing process and the high degree of integration can be satisfied.